Lastwechselmethoden für Siliziumkarbid-MOSFETs unter Berücksichtigung von deren Schwellspannungsinstabilität

Abstract

The application of established qualification test routines like power cycling to SiC MOSFETs is not as straightforward as it may seem: The threshold voltage Vth of SiC MOSFETs is not a stable parameter, affecting junction temperature sensing during the test execution and yielding an undesired shift of the turn-on resistance. Within this work, a Vth-monitoring concept is proposed and applied. Based on this approach, an extensive characterisation of Vth-instabillities under power cyclinge like gate conditions is carried out, the main influencing factors are identified and a concept to suppress parasitic drift effects during a power cycling test based on preconditioning is derived. The comparison of first power cycling results with and without prior applied preconditioning validates this approach and further implicates a significant impact of Vth on the test outcome. In addition, a junction temperarure measurement approach independent on Vth-instabilities based on a chip-integrated sensor is introduced and compared to the established VSD(T)-method. As result of this work, the main challenges of the application of power cycling tests to SiC MOSFETs are pointed out, methods dealing with them are proposed and verified by using special engineering samples as well as commercial SiC MOSFETs of different manufactures and voltage classes as exemplary devices under test.